Engine Architecture

The engine maintains deterministic cadence for synaptic updates, separates UI orchestration from core dynamics, and exposes a compact state for visualization.

Host ↔ Micro Node split

• Host: orchestration, visualization, storage, alert rules.
• Micro Node: fixed-cadence inner loop (spikes→dual-decay→G→blend→score), returns state vector {score, Gf, Gs, regimes, health}.

Cadence & determinism

Inner loop runs at fixed cadence to avoid scheduler jitter; decay integrators and timing-sensitive learning remain stable under load.

State surfaces

• Core: Gf, Gs, G, M, regime flags.
• Aux: liquidity-scaled τ, saturation counters, spike raster.

Boundedness & safety

All updates are clipped to compact domains; saturation curves and smooth nonlinearities avoid explosive growth. Visuals are strictly descriptive.